1. Field of the Invention
The invention relates to a method and apparatus for routing data words between components of a computer system and, more particularly, to a method and apparatus for routing data words between components of a computer system such as the processor, memory and/or input/output devices, whether or not the components are configured to process data words of the same width.
2. Description of Related Art
As is well known to those skilled in the art, a computer system consists of a number of subsystems interconnected by paths that transfer data between the subsystems. Two such subsystems are a central processing unit ("processor") or processor subsystem and a memory and storage subsystem ("memory") which may comprise multiple memory devices. The processor controls the operation of the computer system by executing a sequence of instructions to perform a series of mathematical operations on data. Both the instructions and the data are stored in the computer's memory as binary information, patterns of logical ones and zeros. While the processor and memory represent the most essential subsystems of a computer systems, virtually all computer systems also include any number of input/output ("I/O") devices for the transfer of information into and out of the computer system. The most common I/O devices used with a computer system include a keyboard for entering information and instructions, a video monitor and printer for getting information back out to the user and a disk drive or hard disk for making permanent records of stored information or for running additional software. To install an I/O device in a computer system, the I/O device is connected to an outlet on the computer ("I/O port") which, in turn, provides a path between the I/O device and the computer subsystems.
As is further well known to those skilled in the art, all computer systems further include communications channels or "buses" between the processor, memory and any other subsystems included in a particular computer system. Typically, computer systems are provided with a data bus for carrying data to and from the memory, an address bus for carrying signals used to locate a given memory address and a control bus for carrying timing and control pulses to all subsystems included in a computer system. In addition, the I/O ports are also connected to the buses to link the I/O devices to the computer systems.
Information is transferred between computer components in the form of data words. A data word is a sequence of binary digits or "bits", each bit equivalent to a "1" or a "0". While the size of a data word may vary between computer components of different design, data words are most commonly between 8 and 32 bits in length. In general, as increasingly faster computer systems are sought, the size of data words has increased so that data may be processed in larger units and more bits of data are moved through the system per unit of time. For example, while processor subsystems which used 16 bit words were common only a few years ago, the present state of the art processor subsystems, such as the 80386 and 80486 microprocessors made by Intel Corporation, utilize 32 bit, so-called, double word architectures to handle data faster. Similarly, computer system memory subsystems can now store and handle data in 64 bit units, i.e., four contiguous words of 16 bits each or two contiguous double words of 32 bits each, again for faster access.
Each computer subsystem and/or I/O device which combines to form a computer system is configured to transfer data in units which comprise a specified number of bits. The number of bits which a subsystem or I/O device may process as a single unit is generally referred to as its "data width". When a pair of subsystems, such as a pair of I/O devices or an I/O device and a subsystem are configured to have the same data width, the two are "homogeneous" or "matched" with each other. When the transmitting device outputs data in the same sized units which the receiving device is designed to access, data transfers between homogeneous devices along a connecting bus are relatively simple. If, however, the pair of subsystems, pair of I/O devices or the I/O device and the subsystem are configured with different data widths, the two are "heterogeneous" or "mismatched". As heterogeneous devices cannot address the connecting bus in the same size data units, data transfers between heterogeneous devices are more complicated. Computer systems which are comprised of mismatched subsystems and/or I/O devices result for any number of reasons. For example, the technological developments which have permitted the transmission of data in increasingly larger units are often chronologically unevenly spaced. Thus, while an existing I/O device may have matched an older 8, or even 16, bit processor subsystem, the same I/O device would be mismatched if connected with a newer, 32 bit processor subsystem. As a result, a system designer, in order to benefit from an improvement in the operating speed of one computer subsystem resulting from an improved subsystem which handles larger units of data, would be forced to replace all of the subsystems and I/O devices which could not access the same size of data unit unless there was some way to compensate for the mismatched devices. For example, U.S. Pat. No. 4,716,527 to Graciotti is directed to a device for making a 16 bit data bus microprocessor compatible with peripherals, expansion devices and associated software designed for an 8 bit data bus by providing a bus converter which receives data from the 16 bit data bus and divides the data bus into high and low portions. The low and high portions may then be selectively coupled to the 8 bit data bus. That is, if a 16 bit word from the microprocessor is being transferred to an 8 bit wide external device, the upper and lower portions are selectively coupled to the 8 bit wide external device.
While the connection of a wider data bus to a narrow data bus by means of a data register having a width corresponding to that of the wider data bus and selector circuitry for connecting different portions of the data register to the narrower data bus one at a time in an appropriate sequence may provide a satisfactory operation, such types of interfacing mechanisms can present a bottleneck to the movement of data in other applications. In particular, where multiple data handling units are connected to one side of the interface mechanism and the data handling units on opposite sides of the interface mechanism are not always ready to perform a data transfer at the same moment, then delays may be encountered when one of the multiple units has to wait on the completion of a data transfer for another of the multiple units. Similarly, U.S. Pat. No. 4,309,754 to Dinwiddie, Jr. is directed to a data interface mechanism for interfacing busses of different bit widths. To convert data bytes into plural-byte data words, Dinwiddie, Jr. provides a plurality of-random access (RAM) storage units located between the two data busses and an addressing structure for producing control signals. For successive data transfers to or from the narrower data bus, a series of different chip select signals select the different RAM units, one after the other, in a repeating sequence to transfer successive data bytes. Like Graciotti, however, the repeating access sequence makes Dinwiddie, Jr. particularly inflexible should the relative widths of the interfacing busses change. Furthermore, the chip select signals generated by the Dinwiddie, Jr. circuitry would be unable to transfer data between changing width interface differences.